1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, to a structure for controlling the start timing of the operation of the column decoder in a semiconductor memory device such as a DRAM (dynamic random access memory).
This application is based on Patent Application No. Hei 11-23289 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
When data is read out from a conventional semiconductor memory device such as a DRAM, a sense amplifier operation complete signal indicating the completion of the operation of the sense amplifier is used as a signal for enabling the column decoder for decoding the column address which indicates the data line to which a target memory cell (to be read out) is connected.
FIG. 8 is an operational timing chart for reading out data in the DRAM. This timing chart shows the timing of synchronization clock signals RAS (row address strobe) and CAS (column address strobe), address data, and the data output "D out". In the figure, the period t.sub.RCD indicates a delay time between the synchronization clock signals RAS and CAS, which corresponds to a period from the time when the signal RAS is output to the time when the signal CAS is output. Here, the synchronization clock signal RAS functions as a control signal for determining the timing for confirming the row address data which designates the word line to which the target memory cell is connected, while the synchronization clock signal CAS functions as a control signal for determining the timing for confirming the column address data. The period t.sub.CAC is the CAS access time indicating the period from the time when the synchronization clock signal CAS is output (and the column address is confirmed) to the time when the data is output.
The period t.sub.RAC is the RAS access time indicating the period from the time when the above synchronization clock signal RAS falls to the time when the data is output from the target memory cell. This RAS access time corresponds to the total time of the above delay time t.sub.RCD (between the outputs of RAS and CAS) and the above CAS access time t.sub.CAC.
In addition, period t.sub.RAS indicates the RAS active time, period t.sub.RCS indicates the read command set-up time, and period t.sub.RAD indicates the RAS to column address delay time.
In a conventional semiconductor memory device, the column decoder is made operable after the sense amplifier operation complete signal is output. That is, in the conventional technique, a semiconductor memory device having a long RAS access time t.sub.RAC is controlled to have a long period from the output of the synchronization clock signal RAS to the time when the column decoder becomes operable, so as to have a suitable RAS-CAS delay time t.sub.RCD.
However, in such a conventional semiconductor memory device, the column decoder is always made operable after the sense amplifier operation complete signal is output, regardless of the RAS access time t.sub.RAC ; thus, the time t.sub.RAC is limited by the time for waiting for the sense amplifier operation complete signal.
That is, as shown in FIG. 7, the electric potential of the word line (to which the target memory cell is connected) rises at time t.sub.1, when the row address is confirmed, and the sense enable signal SE for making the sense amplifier operable is output to the sense amplifier at time t.sub.2. As a result, the "data" voltage (corresponding to data 1 or 0) applied to a capacitor in the memory cell is amplified, and a "signal" voltage corresponding to the data voltage is superimposed on the pre-charge voltage and appears in a pair of data (or bit) lines.
The completion timing of the amplifying operation of the sense amplifier has dispersion .DELTA.t according to differences of the manufacturing conditions of each product (i.e., semiconductor memory device); thus, it is necessary to consider a margin .DELTA.tm with respect to the sense amplifier operation complete signal SEEND.
In addition, this sense amplifier operation complete signal SEEND is generated by delaying the synchronization clock signal RAS by a predetermined time, where this delay time may disperse so that a much longer margin may be necessary. Therefore, the RAS access time t.sub.RAC is also limited by the margin .DELTA.tm.